ics331-26 mds 331-26 e 1 revision 051310 integrated device technology, inc. www.idt.com single output clock synthesizer description the ics331-26 is a low cost frequency generator that is factory programmable. using analog/digital phase-locked-loop (pll) techniques, the device accepts a 24 mhz clock input to produce selectable output clocks of 48 mhz and 72 mhz. the device also has a power down feature that tri-states the clock outputs and turns off the plls when the pdts pin is taken low. features ? 8-pin soic package ? pb-free, rohs compliant ? input clock frequency of 24 mhz ? selectable output clocks of 48 mhz or 72 mhz ? spread spectrum ? duty cycle of 45/55 ? operating voltage of 3.3 v ? advanced, low power cmos process block diagram crystal oscillator x1 x2 pll clock synthesis and control circuitry clk pdts (both outputs and pll) 24 mhz crystal or clock otp rom with pll divider values optional crystal capacitors s1:0 2 vdd gnd
single output clock synthesizer mds 331-26 e 2 revision 051310 integrated device technology, inc. www.idt.com ics331-26 pin assignment 8 pin (150 mil) soic output clock selection table pin descriptions external components series termination resistor clock output traces over one inch should use series termination. to series terminate a 50 ? trace (a commonly used trace impedance), place a 33 ? resistor in series with the clock line, as close to the clock output pin as possible. the nominal impedance of the clock output is 20 ? . decoupling capacitor as with any high performance mixed-signal ic, the ics331-26 must be isolated from system power supply noise to perform optimally. a decoupling capacitor of 0.01f must be connected between vdd and the pcb ground plane. crystal load capacitors the device crystal connections should include pads for small capacitors from x1 to ground and from x2 to ground. these capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short pcb traces (and no vias) between the crystal and device. crystal capacitors x1/iclk vdd gnd pdts s0 s1 clk x2 1 2 3 4 8 7 6 5 s1 s0 clk (mhz) spread percentage 0 0 48 1.5% 01 72 1.5% 10 48 1.0% 10 72 1.0% pin number pin name pin type pin description 1 x1 xi connect this pin to a 24 mhz crystal or clock input. 2 vdd power connect to +3.3 v. 3 gnd power connect to ground. 4 s0 input select pin 0 for frequency selection on clk. internal pull-up. 5 clk output clock output per table above. weak internal pull-down when tri-stated. 6 s1 input select pin 1 for frequency selection on clk. internal pull-up. 7pdts input powers down entire chip. tri-states clk outputs when low. internal pull-up. 8 x2 xo float for clock input.
single output clock synthesizer mds 331-26 e 3 revision 051310 integrated device technology, inc. www.idt.com ics331-26 must be connected from each of the pins x1 and x2 to ground. the value (in pf) of these crystal caps should equal (c l -6 pf)*2. in this equation, c l = crystal load capacitance in pf. example: for a crystal with a 16 pf load capacitance, each crystal capacitor would be 20 pf [(16-6) x 2 = 20]. pcb layout recommendations for optimum device performance and lowest output phase noise, the following guidelines should be observed. 1) the 0.01f decoupling capacitor should be mounted on the component side of the board as close to the vdd pin as possible. no vias should be used between decoupling capacitor and vdd pin. the pcb trace to vdd pin should be kept as short as possible, as should the pcb trace to the ground via. distance of the ferrite bead and bulk decoupling from the device is less critical. 2) the external crystal should be mounted just next to the device with short traces. the x1 and x2 traces should not be routed next to each other with minimum spaces, instead they should be separated and away from other traces. 3) to minimize emi the 33 ? series termination resistor, if needed, should be placed close to the clock output. 4) an optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers. other signal traces should be routed away from the ics331-26. this includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. absolute maximum ratings stresses above the ratings listed below can cause permanent damage to the ics331-26. these ratings, which are standard values for idt commercially rated par ts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods can affect product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. recommended operation conditions item rating supply voltage, vdd 7 v all inputs and outputs -0.5 v to vdd+0.5 v ambient operating temperature 0 to +70 c storage temperature -65 to +150 c junction temperature 125 c soldering temperature 260 c parameter min. typ. max. units ambient operating temperature 0 +70 c power supply voltage (measured in respect to gnd) +3.15 +3.3 +3.45 v
single output clock synthesizer mds 331-26 e 4 revision 051310 integrated device technology, inc. www.idt.com ics331-26 dc electrical characteristics unless stated otherwise, vdd = 3.3 v 5% , ambient temperature 0 to +70 c ac electrical characteristics unless stated otherwise, vdd = 3.3 v 5% , ambient temperature 0 to +70 c parameter symbol conditions min. typ. max. units operating voltage vdd 3.15 3.3 3.45 v supply current idd no load, pdts =1 18 ma no load, pdts =0 400 a input high voltage v ih pdts pin vdd-0.5 v input low voltage v il pdts pin 0.4 v input high voltage v ih sel pin 2 v input low voltage v il sel pin 0.4 v input high voltage v ih iclk pin vdd/2+1 v input low voltage v il iclk pin vdd/2-1 v output high voltage (cmos high) v oh i oh = -8 ma vdd-0.4 v output high voltage v oh i oh = -12 ma 2.4 v output low voltage v ol i ol = 12 ma 0.4 v short circuit current i os 70 ma nominal output impedance z o 20 ? internal pull-up resistor r pu s0, s1, pdts pins 360 k ? internal pull-down resistor r pd clk output 510 k ? parameter symbol conditions min. typ. max. units output rise time t or 0.8 to 2.0v, note 1 1.0 ns output fall time t of 2.0 to 0.8v, note 1 1.0 ns duty cycle at vdd/2, note 1 40 60 % cycle jitter (short term jitter) t ja cycle to cycle 150 ps input frequency 24 mhz output enable time pdts high to spread profile stable 3ms output disable time pdts low to tri-state 20 ns
single output clock synthesizer mds 331-26 e 5 revision 051310 integrated device technology, inc. www.idt.com ics331-26 package outline and package dimensions (8 pin soic, 150 mil. body) package dimensions are kept current with jedec publication no. 95 ordering information "lf" suffix to the part number denotes pb-free configuration, rohs compliant. while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) assumes no responsibility for either its use or for the infringemen t of any patents or other rights of third parties, which wou ld result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring ex tended temperature range, high re liability, or other extraordina ry environmental requirements are not recomm ended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or warrant any idt product for use in life support devices o r critical medical instruments. part / order number marking shipping packaging package temperature 331M-26LF 331m26lf tubes 8-pin soic 0 to +70 c 331M-26LFt tape and reel 8-pin soic 0 to +70 c index area 1 2 8 d e seating plane a1 a e - c - b .10 (.004) c c l h h x 45 millimeters inches symbol min max min max a 1.35 1.75 .0532 .0688 a1 0.10 0.25 .0040 .0098 b 0.330.51.013.020 c 0.19 0.25 .0075 .0098 d 4.80 5.00 .1890 .1968 e 3.80 4.00 .1497 .1574 e 1.27 basic 0.050 basic h 5.80 6.20 .2284 .2440 h 0.250.50.010.020 l 0.401.27.016.050 0 8 0 8
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